The term “ground” is probably the most misused and misunderstood term in EMC engineering, and in fact, in all of circuit design. Ground is considered to be a zero potential region with zero resistance and zero impedance at all frequencies. This is just not the case in practical high-speed designs. The one thing that should be remembered whenever the term “ground” is used, is that “Ground is a place where potatoes and carrots thrive!” By keeping this firmly in mind, many of the causes of EMC problems would be eliminated.
The term “ground” is a fine concept at DC voltages, but it just does not exist at the frequencies running on today’s typical boards. All metal has some amount of resistance, and even if that resistance was near zero ohms, the current flowing through a conductor in a loop creates inductance. Current through that inductance results in a voltage drop. This means that the metal ground plane/wire/bar/etc. has a voltage drop across it, which is in direct contradiction with the intention and definition of ground The important point is that for EMI/EMC we need to consider the current, not the voltage, in our signal paths. Since current must always flow in a loop back to its source, the return current path must be considered as well as the intended signal path along a PCB trace. Any interruptions to the return current path can have serious negative effects to
the EMI/EMC performance of a PCB. A very slight deviation in return current path can result in enough inductance to dramatically increase emissions.
The return current path is also very important when considering mother/daughter board configurations. Figure 1 shows a simple four-layer board example of a mother/daughter board configuration and a signal path from the mother board to the daughter card through a connector. If we consider how the return current will flow from this configuration, we should expect that the return current will spread out to include displacement current through the dielectric between GND and PWR, as well as local decoupling capacitors (depending on their distance and the plane separation).
Figure 2 shows the return current for this configuration. The added return current path length results in additional inductance in the total path, resulting in a ‘noise’ voltage between the two GND planes (across the connector). This noise voltage will drive the wide, thin, monopole-like antenna, resulting in increased emissions.
However, if we had simply considered the return current path and routed the signal trace so that it was referenced to the same plane (PWR or GND), the return currents are able to stay close to the signal trace (Figure 3), and emissions are greatly reduced.
When we consider the return current path, more ‘ground’ is not always the ‘right’ answer! For example, on a recent design, there was a 144 pin connector with many high speed signals traveling from one board to the other. It was determined that 30 pins could be used for ‘power’ and ‘ground’ combined. At least five pins must be ‘power’ so there would not be an excessive DC voltage drop across the connector. How many of the remaining 25 pins should be ‘ground’?
In this particular design, it turned out that about 2/3 of the total signal pins were referenced to the ‘power’ plane, and only 1/3 referenced against the ‘ground’ plane. This meant that of the total 30 possible power/ground pins, 2/3 should be ‘power’ and only 1/3 should be ‘ground’! More ‘ground’ pins was NOT the best design for this case. Of course, once we consider both the ‘power’ and the ‘ground’ pins to be return current paths, it is obvious we should distribute them throughout the signal pins to keep the return current deviation as small as possible (compared to putting all the ‘ground’ pins at the ends of the connector, etc.).
When we consider the most important concerns for good EMI/ EMC design, the schematic is not as important as the physical layout of the signal path and the return current. Since today’s high speed PCBs have many layers and are very complex, it is difficult for an engineer to examine each critical signal path for a good return current path. Automated EMC rule checking tools can examine each net in turn, regardless of the PCB complexity. The key to selecting an automated rule checking tool is to make sure it can interface well with your existing design process, it is easy to use, and it can display rule violations in a graphical and easy to understand manner.
The most important EMC design rules for high speed PCBs concern the return current path. Since the return current will always find a path that minimizes the inductance of that path, the return current will always flow on the nearest plane,whether it is called ‘ground’ or ‘power’ or ‘carrots’. When traces across a split in the return plane (for example if a trace is routed next to a power layer with multiple power islands), the return current’s path is interrupted. Changing layers within the PCB so that the return current must also change planes will also interrupt the return current path. Remember, the return current must always get back to its source. It will get back to its source. The only question is whether it will be a path that is beneficial to you, or if it will cause problems. So, “Do you feel lucky today?” It is always best to design ‘on purpose’ rather than ‘by luck’.
About the Author
Dr. Bruce Archambeault is an IBM Distinguished Engineer at IBM in Research Triangle Park, NC and co-founder of Applied EM Technology. He received his BSEE degree from the University of New Hampshire in 1977 and his MSEE degree from Northeastern University in 1981. He received his PhD from the University of New Hampshire in 1997. His doctoral research was in the area of computational electromagnetics applied to real-world EMC problems.
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| Figure 1: Initial two board configuration |
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| Figure 2: Return current paths for initial configuration |
the EMI/EMC performance of a PCB. A very slight deviation in return current path can result in enough inductance to dramatically increase emissions.
The return current path is also very important when considering mother/daughter board configurations. Figure 1 shows a simple four-layer board example of a mother/daughter board configuration and a signal path from the mother board to the daughter card through a connector. If we consider how the return current will flow from this configuration, we should expect that the return current will spread out to include displacement current through the dielectric between GND and PWR, as well as local decoupling capacitors (depending on their distance and the plane separation).
Figure 2 shows the return current for this configuration. The added return current path length results in additional inductance in the total path, resulting in a ‘noise’ voltage between the two GND planes (across the connector). This noise voltage will drive the wide, thin, monopole-like antenna, resulting in increased emissions.
However, if we had simply considered the return current path and routed the signal trace so that it was referenced to the same plane (PWR or GND), the return currents are able to stay close to the signal trace (Figure 3), and emissions are greatly reduced.
When we consider the return current path, more ‘ground’ is not always the ‘right’ answer! For example, on a recent design, there was a 144 pin connector with many high speed signals traveling from one board to the other. It was determined that 30 pins could be used for ‘power’ and ‘ground’ combined. At least five pins must be ‘power’ so there would not be an excessive DC voltage drop across the connector. How many of the remaining 25 pins should be ‘ground’?
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| Figure 3: Improved return current design |
When we consider the most important concerns for good EMI/ EMC design, the schematic is not as important as the physical layout of the signal path and the return current. Since today’s high speed PCBs have many layers and are very complex, it is difficult for an engineer to examine each critical signal path for a good return current path. Automated EMC rule checking tools can examine each net in turn, regardless of the PCB complexity. The key to selecting an automated rule checking tool is to make sure it can interface well with your existing design process, it is easy to use, and it can display rule violations in a graphical and easy to understand manner.
The most important EMC design rules for high speed PCBs concern the return current path. Since the return current will always find a path that minimizes the inductance of that path, the return current will always flow on the nearest plane,whether it is called ‘ground’ or ‘power’ or ‘carrots’. When traces across a split in the return plane (for example if a trace is routed next to a power layer with multiple power islands), the return current’s path is interrupted. Changing layers within the PCB so that the return current must also change planes will also interrupt the return current path. Remember, the return current must always get back to its source. It will get back to its source. The only question is whether it will be a path that is beneficial to you, or if it will cause problems. So, “Do you feel lucky today?” It is always best to design ‘on purpose’ rather than ‘by luck’.
About the Author
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| Dr. Bruce Archambeault |
Dr. Bruce Archambeault is an IBM Distinguished Engineer at IBM in Research Triangle Park, NC and co-founder of Applied EM Technology. He received his BSEE degree from the University of New Hampshire in 1977 and his MSEE degree from Northeastern University in 1981. He received his PhD from the University of New Hampshire in 1997. His doctoral research was in the area of computational electromagnetics applied to real-world EMC problems.
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